Fin field effect transistors (FinFETs) continue to be used more often in semiconductor technology as the size of technology decreases. Unfortunately, FinFETs are generally more susceptible to device failures from electrostatic discharge (ESD) events because of their relatively small channel width. Therefore, a solution is needed to overcome this problem.
FinFETs are considered three-dimensional transistors because of their physical structure. The active area of the FinFET—the drain, channel, and source—protrude up from the surface of the semiconductor substrate upon which the FinFET is located, much like a rectangular box. Also, the gate structure wraps around the channel, usually on three sides but sometimes on two sides.
FinFETs are advantageous in smaller technologies because of their relatively higher drive current when compared to devices of similar size and because of their general ability to prevent short-channel effects. FinFETs generally have increased drive currents because the gate wraps around the channel such that the effective width of the channel is increased. The increased channel width allows for a greater drive current. Further, by having the gate wrap around the channel, the gate can suppress leakage current through the channel more easily, thus decreasing short channel effects.
The advantages of FinFETs have led to their use in smaller technologies, particularly 32 nm and smaller, but the trade-off for smaller size has led to an increased susceptibility of failure for FinFETs during ESD events. The active area width of a FinFET is much smaller than that of another device of corresponding technology size. The smaller width leads to increased current density in the FinFET when an ESD event occurs. For example, FinFETs typically have a maximum of 0.1 mA/μm before device breakdown occurs as compared to approximately 2 mA/μm for planar bulk MOSFETs or approximately 1.4 mA/μm for planar SOI MOSFETs. This increased current density may cause the dielectric gate oxide to breakdown between the active area and the gate causing a short between the gate and the active area. Thus, the FinFET may experience complete failure.
ESD events are generally categorized into three different modes, the Human Body Mode (HBM), the Machine Mode (MM), and the Charged Device Mode (CDM). In HBM, generally a person will have a charge stored on him or her. Then the person will touch a pin on a semiconductor package discharging the stored charged onto the semiconductor chip. Ideally, circuitry within the chip will conduct the current away from the internal devices on the chip and drain the current to ground. HBM is generally the lowest magnitude of voltage of the three modes, but usually the longest in duration. Similar to HBM, in MM, a machine, usually considered to be a metal machine, will have a charge stored on it. The machine will contact a pin of a semiconductor package discharging the stored charge. Again, internal circuitry should conduct the current away from components in the chip and to ground. MM is usually between HBM and CDM in magnitude of voltage and duration. In CDM, a charge will build up on the chip itself. The internal circuitry of the chip attempts to direct the current to some power bus such that the current can then be directed away from other internal devices of the chip and drained away to a pin on the package. CDM is typically the highest voltage magnitude with the shortest duration of discharge.
During this CDM discharge is when FinFETs are most susceptible to device failure because of the high voltage magnitude discharged during the ESD event. Thus, there is a need in the prior art for a device to protect FinFETs during CDM ESD events.